Name
Abstract | ||
|---|---|---|
We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transinf.E93.D.1549 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
SoC test, design for testability, TAM design, transparency, ILP | Design for testing,Computer science,Optimal design,Integer programming,Linear programming,Artificial intelligence,Data flow diagram,Transparency (graphic),Mathematical optimization,System on a chip,Pattern recognition,Algorithm,Test data | Journal |
Volume | Issue | ISSN |
E93D | 6 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 18 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomokazu Yoneda | 1 | 154 | 19.35 |
| Akiko Shuto | 2 | 1 | 0.70 |
| Hideyuki Ichihara | 3 | 96 | 18.92 |
| Tomoo Inoue | 4 | 352 | 47.23 |
| Hideo Fujiwara | 5 | 264 | 28.05 |