Name
Title | ||
|---|---|---|
An access-sequence control scheme to enhance random-access performance of embedded DRAM's |
Abstract | ||
|---|---|---|
An embedded DRAM enables a high data-transfer rate since it provides an on-chip wide-bus interconnection. However, the net data-transfer rate is reduced by page misses because of the inherently large row-access time of DRAM's. We previously proposed a multibank DRAM macro based on a micromodule architecture to overcome this problem. The pipelined access of the DRAM macro is especially useful for r... |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/4.668996 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Random access memory,Frequency,Logic circuits,Computer graphics,Image processing,Integrated circuit interconnections,Application software,History,Multimedia systems,Latches | Journal | 33 |
Issue | ISSN | Citations |
5 | 0018-9200 | 5 |
PageRank | References | Authors |
0.83 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. Ayukawa | 1 | 9 | 3.79 |
| T. Watanabe | 2 | 252 | 51.28 |
| S. Narita | 3 | 17 | 5.45 |