Name
Abstract | ||
|---|---|---|
The VLSI architecture targeted on FPGAs of a multiuser detector based on a cascade of adaptive filters for asynchronous WCDMA systems is presented. The algorithm is briefly described. This paper focuses mainly on real-time implementation. Also, it focuses on a design methodology exploiting the modern technology of programmable logic and overcoming the limitations of commercial tools. The dedicated architecture based on a regular structure of processors and a special structure of memory exploiting FPGA architecture maximizes the processing rate. The proposed architecture was validated using synthesized data in UMTS communication scenarios. The performance goal is to maximize the number of users of different WCDMA data traffics. This dedicated architecture can be used as an intellectual property (IP) core processing an MUD function in the system-on-programmable-chip (SOPC) of UMTS systems. The targeted FPGA components are Virtex-II and Virtex-II Pro families of Xilinx. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1155/ASP/2006/52919 | EURASIP J. Adv. Sig. Proc. |
Keywords | Field | DocType |
umts system,umts communication scenario,dedicated architecture,vlsi architecture,different wcdma data traffic,cascade filter,fpga architecture,processing rate,regular structure,asynchronous wcdma system,fpga implementation,proposed architecture | Asynchronous communication,Architecture,UMTS frequency bands,Computer science,Field-programmable gate array,Multiuser detection,Adaptive filter,Code division multiple access,Embedded system,Programmable logic device | Journal |
Volume | Issue | ISSN |
2006, | 1 | 1687-6180 |
Citations | PageRank | References |
3 | 0.40 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Quoc-Thai Ho | 1 | 6 | 1.19 |
| Daniel Massicotte | 2 | 22 | 2.80 |
| Adel Omar Dahmane | 3 | 24 | 8.77 |