Name
Title | ||
|---|---|---|
High-Speed Continuous-Time Subsampling Bandpass Delta Sigma Ad Modulator Architecture Employing Radio Frequency Dac |
Abstract | ||
|---|---|---|
This paper proposes a continuous-time bandpass Delta Sigma AD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietfec/e89-a.4.916 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | DocType | Volume |
continuous-time, subsampling, bandpass, Delta Sigma modulator, RF DAC, jitter | Journal | E89A |
Issue | ISSN | Citations |
4 | 0916-8508 | 0 |
PageRank | References | Authors |
0.34 | 4 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masafumi Uemori | 1 | 0 | 0.68 |
| Haruo KOBAYASHI | 2 | 14 | 7.37 |
| Tomonari Ichikawa | 3 | 0 | 0.68 |
| Atsushi Wada | 4 | 2 | 2.31 |
| Koichiro Mashiko | 5 | 2 | 2.31 |
| Toshiro Tsukada | 6 | 20 | 4.74 |
| Masao Hotta | 7 | 30 | 9.59 |