Title
Study Of Reducing Circuit Scale Associated With Bit Depth Expansion Using Predictive Gradation Detection Algorithm
Abstract
The authors have evaluated a method of expanding the bit depth of image signals called SGRAD, which requires fewer calculations, while degrading the sharpness of images less. Where noise is superimposed on image signals, the conventional method for obtaining high bit depth sometimes incorrectly detects the contours of images, making it unable to sufficiently correct the gradation. Requiring many line memories is also an issue with the conventional method when applying the process to vertical gradation. As a solution to this particular issue, SGRAD improves the method of detecting contours with transiting gradation to effectively correct the gradation of image signals which noise is superimposed on. In addition, the use of a prediction algorithm for detecting gradation reduces the scale of the circuit with less correction of the vertical gradation.
Year
DOI
Venue
2014
10.1587/transinf.E97.D.1283
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
bit depth expansion, circuit size, IIR filter, gradation pridiction algorithm
Computer vision,Computer science,Infinite impulse response,Algorithm,Color depth,Artificial intelligence,Gradation
Journal
Volume
Issue
ISSN
E97D
5
1745-1361
Citations 
PageRank 
References 
0
0.34
3
Authors
5
Name
Order
Citations
PageRank
Akihiro Nagase100.34
Nami Nakano200.34
Masako Asamura321.60
Jun Someya441.21
Gosuke Ohashi5397.32