Name
Abstract | ||
|---|---|---|
This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118 MHz allows a data throughput rate of 5.9 Gbps. The throughput is about 26% higher, compared to other counterparts. It supports cryptography of high-speed multimedia data. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/elex.6.1174 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
cryptography, secure hash algorithm, hardware design | Throughput (business),SHA-1,Computer science,Cryptography,Parallel computing,Electronic engineering,Hash function,Throughput,Critical path method,Clock rate,Embedded system,Secure Hash Algorithm | Journal |
Volume | Issue | ISSN |
6 | 16 | 1349-2543 |
Citations | PageRank | References |
10 | 0.85 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. H. LEE | 1 | 17 | 2.75 |
| Jehoon Lee | 2 | 37 | 9.61 |
| IlHwan Park | 3 | 38 | 2.48 |
| Kyoung-Rok Cho | 4 | 217 | 31.77 |