Paper Info
Title
Transient fault prediction based on anomalies in processor events
Abstract
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or temporal redundancy to achieve fault tolerance. Though they can provide complete fault coverage, they incur significant hardware and/or performance cost. It is desirable to have mechanisms that can provide partial but sufficiently high fault coverage with negligible cost. To meet this goal, we propose leveraging speculative structures that already exist in modern processors. The proposed mechanism is based on the insight that when a fault occurs, it is likely that the incorrect execution would result in abnormally higher or lower number of mispredictions (branch mispredictions, L2 misses, store set mispredictions) than a correct execution. We design a simple transient fault predictor that detects the anomalous behavior in the outcomes of the speculative structures to predict transient faults.
Year
DOI
Venue
2007
10.1109/DATE.2007.364448
DATE
Keywords
Field
DocType
high fault coverage,simple transient fault predictor,processor event,speculative structure,store set mispredictions,branch mispredictions,transient fault,transient fault prediction,transient error,correct execution,complete fault coverage,fault tolerance,hardware,redundancy,transistors,fault detection,memory footprint,noise reduction,fault coverage,fault tolerant,cmos technology,energy optimization,cmos integrated circuits,symmetric cipher
Symmetric-key algorithm,Stuck-at fault,Fault coverage,Fault detection and isolation,Computer science,Parallel computing,Real-time computing,CMOS,Redundancy (engineering),Fault tolerance,Memory footprint
Conference
ISSN
Citations 
PageRank 
1530-1591
0
0.34
References 
Authors
13
3
Name
Order
Citations
PageRank
Satish Narayanasamy1104044.36
Ayse K. Coskun257333.55
Brad Calder34145251.59