Name
Title | ||
|---|---|---|
A flexible transform processor architecture for multi-CODECs (JPEG, MPEG-2, 4 and H.264) |
Abstract | ||
|---|---|---|
This paper proposes a flexible architecture of the transform processor for multi-CODECs (JPEG, MPEG-2, 4 and H.264). Also the memory control scheme to efficiently store intermediate data is presented. In the proposed architecture, four arrays block process at the same time with 4 parallel process elements and pipelined structure for improving the processing time. For verification, FPGA platform with ARM-9 core is used. The results show that the proposed architecture satisfies the requirements of each CODECS such as JPEG, MPEG-2, 4 and H.264 standard |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693841 | ISCAS |
Keywords | Field | DocType |
jpeg,memory control scheme,arrays block process,h.264 standard,distributed memory systems,arm-9 core,flexible architecture,flexible electronics,mpeg-2,video coding,fpga,transform processor,intermediate data storage,pipelined structure,field programmable gate arrays,multicodec,mpeg-4,video codecs,arithmetic,parallel processing,computer architecture,codecs,mpeg 4,processor architecture,design methodology,transform coding,mpeg 2,satisfiability | Computer science,Field-programmable gate array,Transform coding,JPEG,JPEG 2000,MPEG-4,Codec,Microarchitecture,MPEG-2,Embedded system | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 2 |
PageRank | References | Authors |
0.57 | 1 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ji hwan Park | 1 | 19 | 7.05 |
| Suh Ho Lee | 2 | 13 | 2.96 |
| Kyu-sam Lim | 3 | 9 | 3.14 |
| Jeong Hun Kim | 4 | 18 | 5.01 |
| Suki Kim | 5 | 138 | 39.60 |