Name
Abstract | ||
|---|---|---|
Reconfigurable MPSoCs (Multiprocessor System-on-Chip) could be viable for certain applications niche where the flexibility of FPGAs (Field-Programmable Gate Array) and software is needed, and a small number of units dismiss other silicon options. However, their design complexity is very high, and raises additional problems, i.e. the definition of a suitable programming model, an efficient memory organization, and the need for ways to optimize application performance. In this paper, we propose a complete development process, which addresses these problems by complementing the current SoC (System-on-Chip) development process with additional steps to support parallel programming and software optimization. This work explains systematically problems and solutions to achieve a FPGA-based MPSoC following our systematic flow and offering tools and techniques to develop parallel applications for such systems. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1016/j.compeleceng.2011.09.006 | Computers & Electrical Engineering |
Keywords | Field | DocType |
parallel application,multiprocessor system-on-chip,additional problem,reconfigurable chip,complete development process,parallel programming,software optimization,development process,additional step,suitable programming model,certain applications niche,field programmable gate array,performance,system on chip,chip,programming model | Program optimization,Computer architecture,Programming paradigm,Computer science,Field-programmable gate array,Real-time computing,Multiprocessing,Gate array,Software,Memory organisation,MPSoC | Journal |
Volume | Issue | ISSN |
38 | 3 | 0045-7906 |
Citations | PageRank | References |
0 | 0.34 | 25 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eduard Fernandez-Alonso | 1 | 9 | 1.73 |
| David Castells-Rufas | 2 | 45 | 7.70 |
| Jaume Joven | 3 | 38 | 4.27 |
| Jordi Carrabina | 4 | 139 | 36.98 |