Paper Info
Title
Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor
Abstract
Cyber Physical Systems are composed of many embedded systems which monitor and control the physical processes for tight integrations of computation and physical processes. Such embedded systems require not only real-time capabilities but also high throughput and low power consumption. High throughput is mainly achieved by parallel architectures such as Simultaneous Multithreading (SMT) and Chip Multiprocessor (CMP), and low power consumption is mainly achieved by Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) under the real-time constraint. In this paper, we present a RT-DVFS algorithm called Hetero Efficiency to Logical Processor (HeLP) which can reduce power consumption easily and effectively in prioritized SMT processors. We also present Hetero Efficiency to Logical Processor with Temporal Migration (HeLP-TM) which applies the temporal migration technique to HeLP. Simulation results show that HeLP can reduce power consumption effectively and HeLPTM is more effective than HeLP.
Year
DOI
Venue
2011
10.1109/RTCSA.2011.78
RTCSA (2)
Keywords
Field
DocType
high throughput,dynamic voltage,physical process,low power consumption,logical processor,power consumption,frequency scaling,hetero efficiency,prioritized smt processor,real-time scheduling,present hetero efficiency,embedded system,rt-dvfs algorithm,computer architecture,embedded systems,cyber physical systems,time frequency analysis,hardware,multi threading,real time systems,real time,simultaneous multithreading,process control
Multithreading,Computer science,Scheduling (computing),Multiprocessing,Chip,Real-time computing,Simultaneous multithreading,Cyber-physical system,Frequency scaling,Throughput,Embedded system
Conference
ISSN
Citations 
PageRank 
1533-2306
1
0.46
References 
Authors
12
4
Name
Order
Citations
PageRank
Kei Fujii191.36
Hiroyuki Chishiro2548.96
Hiroki Matsutani357662.07
Nobuyuki Yamasaki433830.45