Name
Abstract | ||
|---|---|---|
This paper presents an embedded FPGA–based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation. Large environments are split into blocks. This approach, together ... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ReConFig.2008.73 | ReConFig |
Keywords | Field | DocType |
temporal partitioning methodology,navigation trajectory,large environment,harmonic potential,embedded fpga,reconfigurable high performance computers,field programmable gate arrays,algorithm design and analysis,logic design,data flow analysis,fpga,fpgas,coprocessors,tabu search,optimization,reconfigurable computing,space exploration | Logic synthesis,Computer architecture,Algorithm design,Computer science,Parallel computing,Field-programmable gate array,Data-flow analysis,Dataflow,Coprocessor,Design space exploration,Tabu search | Conference |
Citations | PageRank | References |
1 | 0.36 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paulo S. Brandao do Nascimento | 1 | 1 | 0.36 |
| Victor W. C. de Medeiros | 2 | 3 | 0.82 |
| Viviane L. S. Souza | 3 | 1 | 0.36 |
| Abner C. Barros | 4 | 1 | 0.36 |
| Manoel Eusebio de Lima | 5 | 29 | 8.12 |