Name
Abstract | ||
|---|---|---|
Negative bias temperature instability (NBTI), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Reducing leakage consumption is one of the major design goals. The gate replacement (GR) technique is an effective way to reduce both the NBTI effect and leakage. This technique, however, has less flexibility because the replaced gate can only produce one output value and careful algorithms are needed to decide the output value of the replaced gate. In this paper, we propose a novel transmission gate-based technique to minimize NBTI-induced degradation and leakage. This technique, which can offer logic 1 for NBTI mitigation and logic 0 for leakage reduction, provides higher flexibility, as compared to the GR technique. Simulation results show that our proposed technique has up to $20\times$ and $2.16\times$, on average, improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19.19% area penalty, combining our technique and the GR can reduce 17.92% of the total leakage power and 32.36% of NBTI-induced circuit degradation. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TCAD.2012.2214478 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
gate replacement,aging optimization,leakage reduction,static timing analysis,leakage power reduction,pmos transistors,semiconductor device reliability,degradation mitigation,leakage consumption,transmission gate,leakage optimization,negative bias temperature instability,transmission gate based technique,nbti mitigation,circuit degradation,switching speed,negative bias temperature instability (nbti),aging,ageing,area penalty,mosfet | Journal | 32 |
Issue | ISSN | Citations |
1 | 0278-0070 | 16 |
PageRank | References | Authors |
0.80 | 15 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ing-Chao Lin | 1 | 153 | 15.96 |
| Chin-Hung Lin | 2 | 45 | 4.26 |
| Kuan-Hui Li | 3 | 20 | 1.24 |