Name
Abstract | ||
|---|---|---|
The purpose of a communication system is to transmit an information-bearing message signal through a channel that separates a transmitter from a receiver. The modulated carrier is often induced and interfered with by various noise sources. The co-channel separation system is a demodulation process function that operates at the same carrier modulation system. Here, we adopted the field-programmable gate array (FPGA) design platform configuration to develop, implement and achieve co-channel separation for an amplitude-locked loop demodulation chip-design digital system with additive white Gaussian noise interference. In this paper, the compact reconfigurable I/O built-in FPGA chip system is integrated and applied to obtain the cross-field relevant integration function for communication and chip-design system via programming in a graphical language. Additionally, the FPGA chip-design system runs all of the program code in hardware and provides high reliability and determinism. This cross-field ideal is adopted to save time and reduce complexity in the design development of a custom circuitry system. The FPGA chip-design system described in this paper is also used to achieve a digital communication chip prototype design model, followed by presentation of the steps necessary for building and program verification. The communication and chip-design concept may provide very useful physical applications for the industry. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1007/s11277-013-1180-2 | Wireless Personal Communications |
Keywords | Field | DocType |
carrier modulation system,amplitude-locked loop,o built-in fpga chip,amplitude-locked loop demodulation chip-design,digital communication chip design,chip-design system,communication system,co-channel separation system,chip-design concept,digital system,fpga chip-design system,custom circuitry system | Transmitter,Demodulation,Computer science,Field-programmable gate array,Communications system,Real-time computing,Chip,Gate array,Integrated circuit design,Additive white Gaussian noise | Journal |
Volume | Issue | ISSN |
72 | 4 | 1572-834X |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gwo-Jia Jong | 1 | 59 | 18.97 |
| Yin-Chih Chen | 2 | 1 | 1.06 |
| Chen-Shen Huang | 3 | 0 | 1.01 |
| Gwo-Jeng Yu | 4 | 7 | 1.39 |
| Gwo-Jiun Horng | 5 | 99 | 23.82 |