Name
Abstract | ||
|---|---|---|
In recent years, domino logic circuits have received much attention as high-speed circuits by taking place of static CMOS circuits. However, in case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noises compared with static CMOS circuits. In particular, crosstalk can induce critical problems. Therefore, we focus our attention on faulty operations induced by crosstalk in CD domino circuits and propose a new fault simulation method. We realize CD domino logic in VHDL and simulate on a VHDL simulator. We performed experiments for the combinational part of some benchmark circuits of ISCAS'89. And fault coverage for random vectors was obtained from s27 to s1494 under the limitation of simulation time. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/DELTA.2002.994595 | Christchurch |
Keywords | Field | DocType |
cd domino logic,logic function,fault simulation method,domino logic circuit,domino logic,static cmos circuit,vhdl simulator,domino circuit,standard domino logic,clock-delayed domino cmos circuits,cd domino circuit,crosstalk faults,fault coverage,crosstalk,combinational circuits,logic simulation,hardware description languages,capacitance,logic circuits,logic gates | Domino logic,Digital electronics,Sequential logic,Pass transistor logic,Computer science,Domino,Real-time computing,Electronic engineering,Resistor–transistor logic,Logic family,Asynchronous circuit | Conference |
ISBN | Citations | PageRank |
0-7695-1453-7 | 1 | 0.39 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuya Shimizu | 1 | 14 | 5.81 |
| Masaya Takamura | 2 | 1 | 0.39 |
| Takanori Shirai | 3 | 1 | 0.39 |
| Noriyoshi Itazaki | 4 | 23 | 6.50 |
| Kozo Kinoshita | 5 | 756 | 118.08 |