Name
Abstract | ||
|---|---|---|
Technological advances along with more complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application characteristics. This approach to bridging the processor/memory performance gap has been studied in the past, but most studies used trace-driven simulation and only looked at L1 caches. Given the changes in hardware and software since these seminal studies, we revisit the general approach: we present a transparent, phase-adaptive mechanism for L2 cache block superloading with minimal hardware complexity, evaluating it on a full-system simulator running 23 SPEC CPU2000 applications run to completion using training inputs. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/PACT.2007.9 | PACT |
Keywords | Field | DocType |
application characteristic,spec cpu2000 application,minimal hardware complexity,cache performance,l2 cache block,phase-adaptive approach,memory performance gap,general approach,full-system simulator,dynamic application behavior,logical cache block size,l1 cache | Computer architecture,Cache invalidation,Cache pollution,Computer science,Cache,CPU cache,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Smart Cache | Conference |
ISSN | ISBN | Citations |
1089-795X | 0-7695-2944-5 | 1 |
PageRank | References | Authors |
0.35 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthew A. Watkins | 1 | 199 | 14.88 |
| Sally A. Mckee | 2 | 1928 | 152.59 |
| Lambert Schaelicke | 3 | 279 | 20.23 |