Paper Info
Title
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard
Abstract
Current secure applications often need encrypted channels with high throughput, of the order of several gigabits per second. This level of performance is usually obtained with a considerable cost in terms of silicon area. In this paper, we present an implementation of the Advanced Encryption Standard based on heavy pipelining and partial unrolling, which is capable of a 10-Gbps throughput when encrypting with 128-bit keys.
Year
DOI
Venue
2011
10.1109/DSD.2011.37
Digital System Design
Keywords
Field
DocType
silicon area,partial unrolling,hardware implementation,10-gigabit throughput,high throughput,10-gbps throughput,128-bit key,low area,current secure application,encrypted channel,heavy pipelining,considerable cost,advanced encryption standard,throughput,radiation detectors,optimization,cryptography,asic,computer architecture,radiation detector,encryption,aes
Computer science,Cryptography,Real-time computing,Encryption,Throughput,Computer hardware,Pipeline (computing),Gigabit,Advanced Encryption Standard,Parallel computing,Communication channel,Application-specific integrated circuit,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4577-1048-3
0
0.34
References 
Authors
10
2
Name
Order
Citations
PageRank
Paolo Maistri124520.35
Regis Leveugle2181.85