Paper Info
Title
Word length selection method for controller implementation on FPGAs using the VHDL-2008 fixed-point and floating-point packages
Abstract
This paper presents a word length selection method for the implementation of digital controllers in both fixed-point and floating-point hardware on FPGAs. This method uses the new types defined in the VHDL-2008 fixed-point and floating-point packages. These packages allow customizing the word length of fixed and floating point representations and shorten the design cycle simplifying the design of arithmetic operations. The method performs bit-true simulations in order to determine the word length to represent the constant coefficients and the internal signals of the digital controller while maintaining the control system specifications. A mixed-signal simulation tool is used to simulate the closed loop system as a whole in order to analyze the impact of the quantization effects and loop delays on the control system performance. The method is applied to implement a digital controller for a switching power converter. The digital circuit is implemented on an FPGA, and the simulations are experimentally verified.
Year
DOI
Venue
2010
10.1155/2010/593264
EURASIP J. Emb. Sys.
Keywords
Field
DocType
word length,design cycle,vhdl-2008 fixed-point,closed loop system,digital circuit,floating-point hardware,word length selection method,controller implementation,digital controller,control system specification,control system performance,floating-point package,fixed point,floating point
Control theory,Digital electronics,Computer science,Floating point,Real-time computing,VHDL,Control system,Fixed point,Computer hardware,Quantization (signal processing),Digital control
Journal
Volume
Issue
ISSN
2010,
1
1687-3963
Citations 
PageRank 
References 
0
0.34
21
Authors
5
Name
Order
Citations
PageRank
I. Urriza1266.92
L. A. Barragan26013.46
D. Navarro33010.13
J. I. Artigas4608.11
O. Lucia515827.96