Name
Title | ||
|---|---|---|
Some Architectural and Compilation Issues in the Design of Hierarchical Shared-Memory Multiprocessors |
Abstract | ||
|---|---|---|
Latency and synchronization overheads have been identified as two fundamental problems in large-scale shared memory multiprocessors. The authors discuss architectures based on hierarchical memories which exploit the notion of partial sharing of variables to significantly reduce latency and synchronization overheads. They examine a particular class of architectures, the tree-structured hierarchical memory multiprocessor architectures (THMM), by suggesting an implementation and considering the compile-time parallelization of nonnested iterative loops with constant dependence distance and unit stride. They compare speedup figures for parallelized loops on the THMM and on a conventional memory multiprocessor. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/IPPS.1992.222966 | IPPS |
Keywords | Field | DocType |
compile-time parallelization,hierarchical shared-memory multiprocessors,constant dependence distance,large-scale shared memory multiprocessors,hierarchical memory,conventional memory multiprocessor,compilation issues,synchronization overhead,tree-structured hierarchical memory multiprocessor,fundamental problem,parallelized loop,nonnested iterative loop,iterative methods,latency,synchronisation,computer architecture,parallel processing,parallel algorithms,tree structure,switches,information science | Computer architecture,Shared memory,Computer science,Parallel computing,Cache-only memory architecture,Distributed memory,Multiprocessing,Conventional memory,Distributed shared memory,Memory architecture,Speedup | Conference |
ISBN | Citations | PageRank |
0-8186-2672-0 | 3 | 0.40 |
References | Authors | |
7 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. N. Jayasimha | 1 | 158 | 16.02 |
| Jeff D. Martens | 2 | 3 | 1.07 |