Name
Abstract | ||
|---|---|---|
This paper compares various contemporary multi-core based microprocessor architectures with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix operations are used as a benchmark application from the area of electrical engineering. Within this context, thread to core pinnning and cache optimization are two important aspects which are investigated in more detail. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-03275-2_5 | PACT |
Keywords | Field | DocType |
core pinnning,various contemporary multi-core,benchmark application,cache optimization,sparse matrix operation,microprocessor architecture,parallel efficiency,sparse matrix operations,multi-core architectures,different memory,important aspect,electrical engineering,multi core,sparse matrices | Computer science,Microprocessor,Parallel computing,Thread (computing),Multi-core processor,Sparse matrix,Cache optimization,Speedup | Conference |
Volume | ISSN | Citations |
5698 | 0302-9743 | 1 |
PageRank | References | Authors |
0.38 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carsten Trinitis | 1 | 151 | 29.80 |
| Tilman Küstner | 2 | 5 | 2.51 |
| Josef Weidendorfer | 3 | 115 | 17.98 |
| Jasmin Smajic | 4 | 7 | 2.13 |