Title | ||
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Study Of The Dc Performance Of Fabricated Magnetic Tunnel Junction Integrated On Back-End Metal Line Of Cmos Circuits |
Abstract | ||
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In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14 mu m CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60 x 180 nm(2) achieves a large change in resistance of 3.52 k Omega (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320 mu A that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device. |
Year | DOI | Venue |
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2010 | 10.1587/transele.E93.C.608 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
magnetic tunnel junction (MTJ), spin-transfer torque RAM (STT-RAM), tunnel magnetoresistance (TMR), magnetoresistive RAM (MRAM), current-induced magnetization switching | Computer science,Spintronics,CMOS,Magnetoresistive random-access memory,Tunnel magnetoresistance,Spin-transfer torque,Electronic circuit,Electrical engineering | Journal |
Volume | Issue | ISSN |
E93C | 5 | 0916-8524 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
9 |
Name | Order | Citations | PageRank |
---|---|---|---|
Fumitaka Iga | 1 | 3 | 2.11 |
Masashi Kamiyanagi | 2 | 4 | 3.17 |
Shoji Ikeda | 3 | 0 | 0.34 |
Katsuya Miura | 4 | 134 | 49.20 |
Jun Hayakawa | 5 | 34 | 23.14 |
Haruhiro Hasegawa | 6 | 3 | 2.11 |
Takahiro Hanyu | 7 | 441 | 78.58 |
Hideo Ohno | 8 | 123 | 33.57 |
Tetsuo Endoh | 9 | 155 | 35.26 |