Name
Title | ||
|---|---|---|
Implementation and evaluation of a (b,k)-adjacent error-correcting/detecting scheme for supercomputer systems |
Abstract | ||
|---|---|---|
This paper describes a coding scheme developed for a specific supercomputer architecture and structure. The code considered is a shortened (b,k)-adjacent single-error-correcting double-error probabilistic-detecting code with b = 5, k = 1, and code group width = 4. An evaluation of the probabilistic double-error-detection capability of the code was performed for drfferent organizations of the coding/decoding strategies for the codewords. This led to the selection of a system organization encompassing the traditional feature of memory data error protection and also providing for the detection of major addressing errors that may result from faults affecting the interconnection network communication modules. The cost of implementation is a limited amount of extra hardware and a negligible degradation in the double-error-detection properties of the code. |
Year | DOI | Venue |
|---|---|---|
1984 | 10.1147/rd.282.0159 | IBM Journal of Research and Development |
Keywords | Field | DocType |
coding scheme,drfferent organization,decoding strategy,extra hardware,interconnection network communication module,supercomputer system,probabilistic double-error-detection capability,double-error-detection property,code group width,adjacent single-error-correcting double-error,adjacent error-correcting,limited amount,error correction,system analysis,error detection | Supercomputer architecture,Supercomputer,Computer science,Network communication,Systems analysis,Parallel computing,Coding (social sciences),Decoding methods,Probabilistic logic,Interconnection | Journal |
Volume | Issue | ISSN |
28 | 2 | 0018-8646 |
Citations | PageRank | References |
1 | 0.41 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jean Arlat | 1 | 1256 | 139.40 |
| W. C. Carter | 2 | 1 | 0.41 |