Name
Abstract | ||
|---|---|---|
An high performance phase-locked-loop (PLL) design method is discussed. In this context high performance means a high order PLL with efficient noise reduction and accurate frequency response achievements. Both analog PLL (APLL) and digital PLL (DPLL) designs may be obtained through the proposed technique. The method allows any order PLL but is especially useful for high-order PLLs because of its difficult design. An explicit formalism for PLL design is established and APLL and DPLL models are also presented. High order design examples are discussed. Experimental results obtained through DPLL realization on a fixed point digital signal processor (DSP) and APLL realization with a commercially available circuit are presented, discussed and compared. Finally, conclusions are drawn. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ISCAS.1999.780025 | Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium |
Keywords | Field | DocType |
circuit feedback,digital phase locked loops,digital signal processing chips,frequency response,network synthesis,network topology,phase detectors,phase locked loops,Butterworth design,DCO/VCO,accurate frequency response achievement,analog PLL,digital PLL,efficient noise reduction,feedback closed loop,fixed point digital signal processor,functional blocks,high order PLL,high performance PLL design,linear model,loop filter,low-pass filter,models,phase detector,phase/frequency divider | Phase-locked loop,Digital signal processing,Digital signal processor,Computer science,Control theory,PLL multibit,Network synthesis filters,Electronic engineering,DPLL algorithm,Low-pass filter,Phase detector | Conference |
Volume | ISBN | Citations |
4 | 0-7803-5471-0 | 7 |
PageRank | References | Authors |
1.24 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. M. Almaida | 1 | 7 | 1.24 |
| Moisés Simões Piedade | 2 | 43 | 14.31 |
| Almeida, T.M. | 3 | 7 | 1.24 |