Paper Info
Title
A Methodology for Mapping SysML Activity Diagram to Time Petri Net for Requirement Validation of Embedded Real-Time Systems with Energy Constraints
Abstract
In this paper we use the Activity diagram of the System Modeling Language (SysML) in combination with the new UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) in order to validate functional, timing and low power requirements in early phases of the embedded system development life-cycle. However, SysML lacks a formal semantics and hence it is not possible to apply, directly, mathematical techniques on SysML models for system validation. Thus, a novel approach for automatic translation of SysML Activity diagram into Time Petri Net with Energy constraints (ETPN) is proposed. In order to depict the practical usability of the proposed method, a case study is presented, namely, pulse-oximeter. Besides, the estimates obtained (execution time and energy consumption) from the model are 95% close to the respective measures obtained from the real hardware platform.
Year
DOI
Venue
2009
10.1109/ICDS.2009.19
Cancun
Keywords
Field
DocType
system modeling,formal semantics,embedded systems,embedded system,data mining,probability density function,real time systems,formal verification,unified modeling language,life cycle,petri nets,activity diagram
Petri net,Unified Modeling Language,Computer science,Usability,Activity diagram,Real-time computing,Systems modeling,Systems Modeling Language,Energy consumption,Formal verification
Conference
ISBN
Citations 
PageRank 
978-0-7695-3526-5
23
1.29
References 
Authors
6
4
Name
Order
Citations
PageRank
Ermeson Andrade19712.29
Paulo Romero Martins Maciel236359.24
Gustavo Callou312416.54
Bruno Nogueira4687.67