Paper Info
Title
A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability
Abstract
This paper describes the silicon architecture of AMD's second generation Macro Array CMOS High Speed/High Density (MACH®) family of PLDs. With an advanced 0.65um technology and an innovative architecture, the next generation MACH family offers gale density up to 10,000+ gates with 100% routability, flexibility, and predictable worst-case pin-to-pin delays of 15ns.
Year
DOI
Venue
1994
10.1007/3-540-58419-6_105
FPL
Keywords
Field
DocType
high density,complex pld family
Predictability,Architecture,Computer science,Parallel computing,High density,Real-time computing,CMOS,Product term,Logic block,Macro,Mach number
Conference
ISBN
Citations 
PageRank 
3-540-58419-6
0
0.34
References 
Authors
1
1
Name
Order
Citations
PageRank
Om P. Agrawal161.53