Name
Title | ||
|---|---|---|
Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology |
Abstract | ||
|---|---|---|
As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint reliability for large chip sizes of up to 100mm2 without underfill is still an issue that needs to be resolved. For solving this problem, a double-layer WLCSP (DL-WLCSP) with both a stress compliant layer and dummy solder joints is proposed in this research to enhance the solder joint fatigue life. Moreover, a hybrid method is employed to predict the profile of solder joint after reflow process. To ensure the correctness of the methodology of the analysis, a Rambus DRAM layout is implemented as the test vehicle to demonstrate the applicability and reliability of the DL-WLCSP. The results of the thermal cycling experimental test show good agreement with the simulated analysis. In addition, besides the geometrical design parameters of the silicon die thickness and the thickness of the stress compliant layer, the reliability impact for the arrangement of die-side and substrate-side pad diameter is investigated by means of the design of experiment (DOE). In addition, the Response Surface Methodology (RSM) with central composite designs (CCD) is adopted to obtain the parameter sensitivity information by the three-dimensional nonlinear finite element analysis (FEA). Analysis of variance (ANOVA) is conducted to determine the significance of the fitted regression model. The analytic results reveal that the stress compliant layer and the dummy joints can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. The smaller thermal strains can be controlled through better size combination between die-side and substrate-side pad diameter. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1016/j.microrel.2006.09.004 | Microelectronics Reliability |
Keywords | Field | DocType |
response surface methodology,central composite design,three dimensional,thermal cycling,stress concentration,analysis of variance,chip,ccd,double layer,coefficient of thermal expansion,regression model,design of experiment,wlcsp | Flip chip,Wafer-level packaging,Electronic packaging,Electronic engineering,Soldering,Temperature cycling,Reflow soldering,Engineering,Die (integrated circuit),Chip-scale package | Journal |
Volume | Issue | ISSN |
47 | 2 | 0026-2714 |
Citations | PageRank | References |
1 | 0.41 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chang-Chun Lee | 1 | 1 | 0.75 |
| Chien-Chen Lee | 2 | 1 | 0.41 |
| Hsiao-Tung Ku | 3 | 1 | 0.75 |
| Shu-ming Chang | 4 | 30 | 8.19 |
| Kuo-Ning Chiang | 5 | 19 | 7.35 |