Name
Abstract | ||
|---|---|---|
This paper proposes an analog LDPC decoder employing new stopping iteration method. It is based on the min-sum algorithm and by checking parity H-matrix to decide iteration termination. The proposed method not only can increase the decoding throughput but also decrease the power consumption. Experimental results show that this decoder can save 90% power consumption speed ratio compared with traditional decoders. Finally, an analog (32, 8) min-sum decoder with new stopping iteration method is implemented by TSMC 0.18μm 1P6M CMOS technology. When the data throughput and supply voltage is 216 Mb/s and 1.8V respectively, the power consumption is only 4.98 mW. This analog decoder has low power and small area characteristics that can be applicable to green communication devices. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/GreenCom-iThings-CPSCom.2013.69 | GreenCom/iThings/CPScom |
Keywords | Field | DocType |
cmos analogue integrated circuits,ldpc,data throughput,power consumption speed ratio,stopping iteration method,ic design,power consumption,low-power analog ldpc decoder,min-sum algorithm,iteration termination,power 4.98 mw,employing new stopping iteration,low-power electronics,analog ldpc decoder,voltage 1.8 v,parity h-matrix,tsmc 1p6m cmos technology,traditional decoder,size 0.18 mum,green communication device,analog decoder,stopping iteration,iteration method,integrated circuit design,min-sum decoder,low power,iterative decoding,parity check codes,low power electronics | Low-density parity-check code,Computer science,Iterative method,Voltage,Electronic engineering,CMOS,Real-time computing,Integrated circuit design,Soft-decision decoder,Throughput,Low-power electronics | Conference |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Ta Lee | 1 | 16 | 5.45 |
| Sheng-Sung Chiu | 2 | 0 | 0.34 |
| Yu-Shi Ke | 3 | 0 | 0.34 |