Name
Title | ||
|---|---|---|
Contention reduced/conditional discharge flip-flops for level conversion in CVS systems |
Abstract | ||
|---|---|---|
Clustered Voltage Scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the efficient level converter with fewer overheads in power and delay. Several novel level conversion flip-flops (LCFF) are proposed: a single-ended contention reduced LCFF (CR-LCFF) and double-ended conditional discharge LCFFs (CD-LCFF). Novel circuit techniques are employed for reducing the LCFF overhead, including conditional discharge technique which effectively suppresses dynamic power, contention reduce technique which suppresses short circuit power in DCVSL circuits during transition. A new pulse generator with 10 transistors is used in the proposed LCFFs. In view of PDP, the new LCFFs outperform previous published designs by about 37.7%-41%. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329360 | ISCAS (2) |
Keywords | Field | DocType |
conditional discharge technique,logic simulation,integrated circuit modelling,power dissipation,convertors,clustered voltage scaling,delay circuits,pulse generator,discharges (electric),level conversion flip-flops,dcvsl circuits,single-ended contention reduced lcff,short circuit power,cmos logic circuits,logic design,integrated circuit design,pulse generators,pulse transformers,double-ended conditional discharge lcff,dynamic power,flip-flops,level converter,switches,low voltage,master slave,circuits | Logic synthesis,Computer science,Voltage,Electronic engineering,Dynamic demand,Integrated circuit design,Logic simulation,Pulse generator,Low voltage,Electronic circuit | Conference |
Volume | ISBN | Citations |
2 | 0-7803-8251-X | 3 |
PageRank | References | Authors |
0.50 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peiyi Zhao | 1 | 96 | 9.81 |
| Golconda Pradeep Kumar | 2 | 10 | 1.43 |
| Magdy Bayoumi | 3 | 190 | 36.91 |