Name
Abstract | ||
|---|---|---|
Different approaches have been developed to mitigate the state space explosion of model checking techniques. Among them, symbolic verification techniques use efficient representations such as BDDs to reason over sets of states rather than over individual states. Unfortunately, past experience has shown that these techniques do not work well for loosely-synchronized models. This paper presents a new algorithm and a new tool that combines BDD-based model checking with partial order reduction (POR) to allow the verification of models featuring asynchronous processes, with significant performance improvements over currently available tools. We start from the ImProviso algorithm (Lerda et al.) for computing reachable states, which combines POR and symbolic verification. We merge it with the FwdUntil method (Iwashita et al.) that supports verification of a subset of CTL. Our algorithm has been implemented in a prototype that is applicable to action-based models and logics such as process algebras and ACTL. Experimental results on a model of an industrial application show that our method can verify properties of a large industrial model which cannot be handled by conventional model checkers. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-642-03240-0_9 | FMICS |
Keywords | Field | DocType |
process algebra,model checking,partial order reduction | Abstraction model checking,Asynchronous communication,Programming language,Model checking,Computer science,Binary decision diagram,Theoretical computer science,Partial order reduction,State space,Process calculus,Symbolic trajectory evaluation | Conference |
Volume | ISSN | Citations |
5596 | 0302-9743 | 4 |
PageRank | References | Authors |
0.51 | 22 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| José Vander Meulen | 1 | 6 | 1.57 |
| Charles Pecheur | 2 | 284 | 28.50 |