Name
Abstract | ||
|---|---|---|
A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18 mu m CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.8.1248 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
MSTP, ASIC, ERST, HLB | CMOS,Application-specific integrated circuit,Electronic engineering,Chip,Integrated circuit design,Engineering,Transistor,Integrated circuit,Dynamic simulation,Design cycle,Embedded system | Journal |
Volume | Issue | ISSN |
E89C | 8 | 0916-8524 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peng Wang | 1 | 0 | 0.68 |
| Chao Zhang | 2 | 351 | 63.97 |
| Nan Hua | 3 | 4 | 1.87 |
| Depeng Jin | 4 | 2177 | 154.29 |
| Lieguang Zeng | 5 | 752 | 56.75 |