Title
Simulating spin systems on IANUS, an FPGA-based computer
Abstract
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
Year
DOI
Venue
2007
10.1016/j.cpc.2007.09.006
Computer Physics Communications
Keywords
DocType
Volume
05.10.Ln,05.10.-a,07.05.Tp,07.05.Bx
Journal
178
Issue
ISSN
Citations 
3
0010-4655
12
PageRank 
References 
Authors
1.93
0
18