Name
Title | ||
|---|---|---|
New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM |
Abstract | ||
|---|---|---|
The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISLPED.2011.5993640 | ISLPED |
Keywords | Field | DocType |
coarse-grained power,power aware computing,power control,new fpga architecture,power consumption,dynamic power gating,region-based fpga architecture,fpga architecture,technology cad (electronics),different region size,low-power electronics,proposed architecture,power aware placement,cad framework,normal architecture,power control hard macro based coarse-grained power gating,placement algorithm,dynamic power,field programmable gate arrays,new power-aware placement,pchm,sleep region,placement,logic gate,logic gates,field programmable gate array,benchmark testing,region,low power electronics,strontium | Logic gate,Computer science,Power control,Field-programmable gate array,Electronic engineering,Application-specific integrated circuit,Real-time computing,Dynamic demand,Power gating,Benchmark (computing),Embedded system,Low-power electronics | Conference |
ISSN | ISBN | Citations |
Pending E-ISBN : 978-1-61284-659-0 | 978-1-61284-659-0 | 5 |
PageRank | References | Authors |
0.44 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ce Li | 1 | 56 | 9.28 |
| Yiping Dong | 2 | 8 | 1.84 |
| Takahiro Watanabe | 3 | 29 | 15.61 |