Name
Abstract | ||
|---|---|---|
We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two- and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that includes a high-resolution fractional divider to reduce quantization noise from a delta-sigma modulator. The SSCG with the two-slope-PWL modulation profile was fabricated in a 0.18 $\mu{\rm m}$ 1P4M CMOS technology. The measured peak power reduction level of the two-slope-PWL modulation profile is 14.2 dB with 5000 ppm down spreading at 1.5 GHz. The SSCG occupies an active area of 0.49 ${\rm mm}^{2}$ and consumes 40 mW of power at 1.5 GHz. The SSCG with the three-slope-PWL modulation profile was fabricated in a 0.13 $\mu{\rm m}$ 1P6M CMOS technology. The measured peak power reduction level of the three-slope-PWL modulation profile is 10.3 and 10.52 dB with 5000 ppm down spreading at 162 and 270 MHz, respectively. The SSCG occupies an active area of 0.096 ${\rm mm}^{2}$ and dissipates 1 mW of power at 270 MHz. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2210290 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
electromagnetic interference (emi) reduction,three-slope-pwl modulation profile,power 40 mw,spread spectrum clock generation (sscg),delta-sigma modulator,piecewise linear approximation,quantisation (signal),spread spectrum control profile generator,phase-locked loop (pll),two-slope-pwl modulation profile,frequency 1.5 ghz,delta-sigma modulation,cmos integrated circuits,sscg,clocks,size 0.18 mum,phase locked loops,peak power reduction level,spread spectrum clock generator,phase-locked loop,high-resolution fractional divider,electromagnetic interference,piecewise linear modulation profile,piecewise linear techniques,size 0.13 mum,cmos technology,quantization noise,frequency 270 mhz,frequency 162 mhz,power 1 mw,delta sigma modulation,phase locked loop,delta sigma modulator,generators,quantization,frequency modulation | Phase-locked loop,Electromagnetic interference,Electronic engineering,CMOS,Delta-sigma modulation,Modulation,Quantization (signal processing),Piecewise linear function,Mathematics,Spread spectrum | Journal |
Volume | Issue | ISSN |
21 | 7 | 1063-8210 |
Citations | PageRank | References |
4 | 0.42 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Minyoung Song | 1 | 40 | 6.89 |
| Sung-Hoon Ahn | 2 | 65 | 15.09 |
| Inhwa Jung | 3 | 70 | 11.23 |
| Yong-tae Kim | 4 | 206 | 31.51 |
| Chulwoo Kim | 5 | 397 | 74.58 |