Name
Abstract | ||
|---|---|---|
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a medium-sized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (SirSim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a special-purpose verification methodology. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICCAD.1999.810706 | ICCAD |
Keywords | Field | DocType |
custom cmos circuit,exponential number,traditional simulation method,standard circuit structure,symbolic simulation,timing verification,larger circuit,industrial design,medium-sized modern logic block,input combination,transistor-level circuit,static analysis,electromagnetics,formal verification,logic simulation | Symbolic simulation,Computer science,Electromagnetics,Static analysis,Electronic engineering,CMOS,Logic simulation,Logic block,Electronic circuit,Formal verification | Conference |
ISBN | Citations | PageRank |
0-7803-5832-5 | 7 | 0.81 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Clayton B. McDonald | 1 | 15 | 2.65 |
| Randal E. Bryant | 2 | 9204 | 1194.64 |