Paper Info
Title
Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls
Abstract
In this paper we model a thread's throughput, the instruction per cycle rate (IPC rate), running on a general microprocessor as used in common embedded systems. Our model is not limited to a particular microprocessor because our aim is to develop a general model which can be adapted thus fitting to different microprocessor architectures. We include stalls caused by different pipeline obstacles like data dependencies, branch misprediction etc. These stalls involve latency clock cycles blocking the processor. We also describe each kind of stall in detail and develop a statistical model for the throughput including the entire processor pipeline.
Year
DOI
Venue
2009
10.1007/978-3-642-10265-3_8
SEUS
Keywords
Field
DocType
general model,cycle rate,different pipeline obstacle,general microprocessor,different microprocessor architecture,ipc rate,analyzing pipeline stalls,common embedded system,particular microprocessor,statistical model,entire processor pipeline,instructions per cycle,embedded system
Instructions per cycle,Pipeline (computing),Computer science,Latency (engineering),Microprocessor,Branch misprediction,Real-time computing,Thread (computing),Statistical model,Throughput,Embedded system
Conference
Volume
ISSN
Citations 
5860
0302-9743
3
PageRank 
References 
Authors
0.42
9
3
Name
Order
Citations
PageRank
Uwe Brinkschulte141252.57
Daniel Lohn270.87
Mathias Pacher310713.21