Name
Abstract | ||
|---|---|---|
This paper describes a method of optimally sizing digital cir- cuits on a static-timing basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradient-based, nonlinear optimization and can ac- commodate transistor-level schematics without the need for pre-characterization. It employs efficient time-domain simu- lation and gradient computation for each channel-connected component. A large-scale, general-purpose, nonlinear op- timization package is used to solve the tuning problem. A prototype tuner has been developed that accomm odates com- binational circuits consisting of parameterized library cells. Numerical results are presented. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1145/309847.309979 | DAC |
Keywords | Field | DocType |
static-timing formulation,custom circuit,gradient-based optimization,logic,combinational circuit,combinational circuits,prototypes,logic simulation,packaging,nonlinear optimization,application specific integrated circuits,logic design,computational modeling,connected component,digital circuits,time domain,leakage | Logic synthesis,Digital electronics,Computer science,Nonlinear programming,Application-specific integrated circuit,Schematic,Electronic engineering,Combinational logic,Logic simulation,Electronic circuit | Conference |
ISBN | Citations | PageRank |
1-58113-109-7 | 56 | 7.37 |
References | Authors | |
15 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. R. Conn | 1 | 56 | 7.37 |
| Ibrahim M. Elfadel | 2 | 153 | 40.15 |
| W. W. Molzen, Jr. | 3 | 56 | 7.37 |
| P. R. O'Brien | 4 | 56 | 7.37 |
| P. N. Strenski | 5 | 56 | 7.37 |
| C. Visweswariah | 6 | 81 | 10.04 |
| C. B. Whan | 7 | 56 | 7.37 |