Title
Reliable NoC architecture utilizing a robust rerouting algorithm
Abstract
Moving towards reconfigurability is an approach to increase fault tolerance on System-on-Chip design. In this paper, we propose a self-reconfigurable NoC architecture utilizing a robust rerouting method. At first, an offline test strategy for locating system-level faults in NoC switch ports is utilized. Using the information achieved in the test phase, every switch reconfigures itself to avoid routing packets through faulty links by utilizing our local rerouting method. The proposed rerouting method is evaluated using a Transaction-Level platform. Experimental results show that our proposed rerouting method delivers all the packets in a faulty NoC successfully and has a less communication overhead compared to a pure flooding method.
Year
DOI
Venue
2008
10.1109/EWDTS.2008.5580142
EWDTS
Keywords
Field
DocType
switches,noc switch ports,integrated circuit testing,integrated circuit reliability,robust rerouting algorithm,reconfigurable architectures,fault tolerance,offline test strategy,integrated circuit design,system-on-chip design,system-level fault location,self-reconfigurable noc architecture,fault location,transaction-level platform,network-on-chip,routing,network on chip,computer architecture,system on a chip,fault tolerant,system on chip
Architecture,System on a chip,Reconfigurability,Computer science,Network packet,Network on a chip,Integrated circuit design,Fault tolerance,Test strategy,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4244-3403-9
5
0.45
References 
Authors
13
5
Name
Order
Citations
PageRank
Armin Alaghi138129.52
Mahshid Sedghi2322.75
Naghmeh Karimi316821.98
Mahmood Fathy448263.71
Zainalabedin Navabi530351.08