Paper Info
Title
A programmable online/off-line built-in self-test scheme for RAMs with ECC
Abstract
Embedded memory plays an important role in modern system-on-chip designs. However, the reliability issue of embedded memories becomes more and more critical with the shrinking of transistor feature size. This paper proposes a programmable online/off-line built-in self-test (BIST) scheme for random access memories (RAMs) with error correction code (ECC). The BIST scheme can be used for performing production testing and periodic transparent testing. In comparison with an existing transparent BIST scheme, the proposed BIST scheme does not incur the aliasing problem. Also, it can provide good fault location capability in online test mode. Experimental results show that the area cost of the proposed online/off-line BIST scheme is low-only about 2.6% for a 4Ktimes39-bit SRAM.
Year
DOI
Venue
2009
10.1109/ISCAS.2009.5118183
ISCAS
Keywords
Field
DocType
error correction code,circuit reliability,production testing,random access memories,sram chips,transistor,error correction codes,built-in self test,ram,programmable online built-in self-test scheme,off-line built-in self-test scheme,sram,system-on-chip design,fault location capability,periodic transparent testing,embedded memory,fault location,circuit testing,testing,production,system on a chip,reliability,system on chip,transistors
Computer science,Circuit reliability,Static random-access memory,Electronic engineering,Error detection and correction,Aliasing,Transistor,Embedded system,Built-in self-test,Embedded memory,Random access
Conference
ISBN
Citations 
PageRank 
978-1-4244-3828-0
0
0.34
References 
Authors
12
2
Name
Order
Citations
PageRank
Hsing-Chen Lu100.34
Jin-Fu Li266259.17