Name
Abstract | ||
|---|---|---|
In this work, we propose a testing technique for detecting single stuck-at and bridging faults in the interconnects of the cluster based FPGA. The presence of the feedback-bridging fault, race and glitch poses major challenges to the detection of the fault. The feedback bridging fault has a high ingredient of delay dependent properties due to the variation of the feedback path delay. So we have exploited the concept of asynchronous logic in order to detect the fault. We configure the block under test (BUT) with a pseudo delay independent asynchronous element known as Muller C element. The novelty of this scheme lies in the fact that, it can detect the stuck-at and bridging fault including the feedback bridging fault by a single test configuration. The Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER (Built-in-self-tester) structure in the FPGA. In comparison to the traditional FPGA development tool (ISE), 'Jbits' gives more controllability for which the partial run time reconfiguration of the FPGA is easily achieved. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1016/j.compeleceng.2013.08.009 | Computers & Electrical Engineering |
Keywords | Field | DocType |
asynchronous logic,single stuck-at,pseudo delay,delay dependent property,feedback-bridging fault,feedback path delay,muller c element,fault detection,independent asynchronous element,traditional fpga development tool,xilinx jbits | Stuck-at fault,Glitch,Computer science,Bridging fault,Bridging (networking),Field-programmable gate array,Real-time computing,Asynchronous circuit,Control reconfiguration,C-element,Embedded system | Journal |
Volume | Issue | ISSN |
39 | 8 | 0045-7906 |
Citations | PageRank | References |
0 | 0.34 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nachiketa Das | 1 | 6 | 2.20 |
| Pranab Roy | 2 | 47 | 14.15 |
| Hafizur Rahaman | 3 | 368 | 91.37 |