Title
Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional Evaluation.
Abstract
A prototype of the Channel chip of the FERMI microsystem has been designed and fabricated (version I, 1994), being currently under test (1995-96). Future implementations (version II, 1996) require a structural refinement and a reduction of dimension of the chip. These modifications require in turn a redistribution and a redesign of the implemented fault tolerance features. In this paper guide-lines for this task are presented and a proposal is discussed.
Year
DOI
Venue
1996
10.1109/DFTVS.1996.572031
DFT
Keywords
Field
DocType
future implementation,paper guide-lines,fault tolerance feature,fermi microsystem,functional evaluation,fault tolerance,new version,structural refinement,channel chip,fermi channel chip,version ii,industrial electronics,large hadron collider,prototypes,chip,data acquisition,physics,fault tolerant,redundancy
Fermi Gamma-ray Space Telescope,Microsystem,Nuclear electronics,Computer science,Data acquisition,Communication channel,Electronic engineering,Chip,Fault tolerance,Very-large-scale integration,Embedded system
Conference
ISBN
Citations 
PageRank 
0-8186-7545-4
1
0.44
References 
Authors
4
2
Name
Order
Citations
PageRank
Anna Antola1588.33
Luca Breveglieri261350.68