Name
Abstract | ||
|---|---|---|
This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages and resolve significant challenges with receiver input and transmitter output insertion loss, power integrity, ESD, and reliability. The transceiver clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The receiver front-end utilizes a 3-stage CTLE with wide input common-mode to remove the post-cursor ISI. The CTLE is fully adaptive using an LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The transceiver achieves BER 10-15 at 6.6 Gb/s over a 20 dB loss channel. Power consumption is 129 mW from 1.2 V and 1 V supplies. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2274824 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS integrated circuits,adaptive equalisers,continuous time systems,electrostatic discharge,field programmable gate arrays,integrated circuit packaging,integrated circuit reliability,lead bonding,low-power electronics,phase locked loops,transceivers,3-tap FIR transmitter,ESD,LMS algorithm,continuous-time linear equalizer,edge-based equalization,enhanced clocking flexibility,field-programmable gate array,flip-chip packages,fully-adaptive low-power quad transceiver,low-leakage CMOS FPGAs,low-power wireline transceiver,power 129 mW,power integrity,receiver front-end,receiver input insertion loss,reliability,ring-based PLLs,size 28 nm,transceiver clocking network,transmitter output insertion loss,voltage 1 V,voltage 1.2 V,wire-bond packages,Adaptive equalizers,clocks,field programmable gate arrays,high-speed integrated circuits,phase locked loops,receivers,ring oscillators,transceivers,transmitters,wideband | Phase-locked loop,Transmitter,Wireline,Transceiver,Computer science,Power integrity,CMOS,Electronic engineering,Insertion loss,Low-power electronics | Journal |
Volume | Issue | ISSN |
48 | 11 | 0018-9200 |
Citations | PageRank | References |
4 | 0.62 | 6 |
Authors | ||
14 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jafar Savoj | 1 | 154 | 27.84 |
| Kenny C.-H. Hsieh | 2 | 39 | 5.37 |
| Fu-Tai An | 3 | 65 | 10.10 |
| Gong, J. | 4 | 4 | 0.62 |
| Jay Im | 5 | 59 | 10.26 |
| Xuewen Jiang | 6 | 32 | 5.13 |
| A. P. Jose | 7 | 21 | 2.03 |
| V. Kireev | 8 | 4 | 0.62 |
| Siok-Wei Lim | 9 | 12 | 1.48 |
| A. Roldan | 10 | 4 | 0.62 |
| D. Z. Turker | 11 | 4 | 0.62 |
| Parag Upadhyaya | 12 | 96 | 16.75 |
| Daniel Wu | 13 | 39 | 5.66 |
| Ken Chang | 14 | 133 | 23.31 |