Name
Title | ||
|---|---|---|
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746235 | ISSCC |
Keywords | Field | DocType |
logic gates,power budget,pll,system on chip,first order,phase locked loops,phase lock loop,system on a chip,jitter,frequency control,generators,switches,soc,cmos integrated circuits,phase locked loop | Power budget,Phase-locked loop,Logic gate,System on a chip,Computer science,PLL multibit,CMOS,Electronic engineering,Process variation,Jitter,Embedded system | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyung-Jin Lee | 1 | 73 | 12.71 |
| Alexandra M. Kern | 2 | 60 | 13.80 |
| Sami Hyvonen | 3 | 14 | 3.23 |
| Ian A. Young | 4 | 94 | 21.40 |