Name
Abstract | ||
|---|---|---|
Programmable, high throughput domain specific cryptoprocessors are required for different networkingapplications. This paper presents the architectural designfeatures that lead to a multiple Gbits/s rate AEScoprocessor, which is programmable with domainspecific instructions for Gbit throughput IPSec and otherapplications. Our design is a loosely coupled,independently working crypto-coprocessor that runs AESin ECB, CBC-MAC, Counter, and CCM modes ofoperation at a maximum throughput of 3.43 Gbits/s in a0.18-驴m CMOS technology without any penalty inthroughput for any of the above modes. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ITCC.2004.1286703 | ITCC (2) |
Keywords | Field | DocType |
different networkingapplications,architectural designfeatures,gbit throughput ipsec,aesin ecb,programmable high throughput aes,m cmos technology,domainspecific instruction,maximum throughput,architectural design features,multiple gbits,ccm modes ofoperation,high throughput domain,instruction sets,assembly,cmos integrated circuits,cmos technology,cryptography,coprocessors,ccm mode,security,throughput,high throughput | IPsec,Gigabit,Cryptography,Computer science,Instruction set,CMOS,CCM mode,Coprocessor,Throughput,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-2108-8 | 7 | 1.04 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alireza Hodjat | 1 | 329 | 22.91 |
| Patrick Schaumont | 2 | 1552 | 149.27 |
| Ingrid Verbauwhede | 3 | 4650 | 404.57 |