Title
Design planning for high-performance ASICs
Abstract
Design planning is emerging as a solution to some of the most difficult challenges of the deep-submicron VLSI design era, Reducing design turnaround time for extremely large designs with ever-increasing clock speeds, while ensuring first-pass implementation success, is exhausting the capabilities of traditional design tools. To solve this problem, we have designed and implemented a hierarchical design planning system that consists of a tightly integrated set of design and analysis tools, The integrated run-time environment, with its rich set of hierarchical, timing-driven design planning and implementation functions, provides an advanced platform for realizing a variety of ASIC and custom methodologies, One of the system's particular strengths is its tight integration with an incremental, static timing engine that assists in achieving timing closure in high-performance designs, The design planner is in production use at IBM internal and at external ASIC design centers.
Year
DOI
Venue
1996
10.1147/rd.404.0431
IBM Journal of Research and Development
Keywords
Field
DocType
design planning,high-performance asics
IBM,Computer science,Circuit design,Application-specific integrated circuit,Design flow,Real-time computing,Turnaround time,Physical design,Very-large-scale integration,Timing closure
Journal
Volume
Issue
ISSN
40
4
0018-8646
Citations 
PageRank 
References 
17
3.76
5
Authors
16
Name
Order
Citations
PageRank
J. Y. Sayah1173.76
rajiv gupta24301364.53
D. D. Sherlekar3173.76
P. S. Honsinger4365.98
J. M. Apte5173.76
S. W. Bollinger6173.76
H. H. Chen7536.37
S. DasGupta8174.10
E. P. Hsieh98859.09
A. D. Huber10173.76
E. J. Hughes11173.76
Z. M. Kurzum12173.76
V. B. Rao1311415.94
T. Tabtieng14173.76
V. Valijan15173.76
D. Y. Yang16173.76