Paper Info
Title
Rothko: A three dimensional FPGA architecture, its fabrication, and design tools
Abstract
1. Abstract We a re designing and p lan to fabricate a 3-dimensional field p rogrammable gate a rray. The three dimensional technology, developed at Northeastern University, is based on transferred circuits with interconnections between layers of active devices. Interconnections are in metal, and can b e placed anywhere on the chip. Our FPGA architecture, called Rothko, extends the Routing and Logic Block (RLB) model developed for the Triptych architecture (1). This model is similar to a sea-of-gates model where individual cells can be used for routing or logic. We extend this to three dimensions by adding connections to each RLB from above and below. This makes our architecture truly 3-D with each logic block having connections to logic blocks on other layers. In this paper we present the architecture of a two layer RLB, discuss the 3-D technology we use, and discuss CAD tools for mapping designs onto Rothko. 2. Introduction To achieve new levels of integration and utilization in field programmable logic requires new FPGA architectures. Problems with existing architectures include low utilization of resources, routing congestion, high delay due to interconnect and insufficient I/O. In this paper we present a novel 3-D FPGA architecture aimed at solving some of these problems. One of the main obstacles to mapping large designs onto existing FPGA architectures is routing congestion. FPGA routing resources are more e xpensive than ASICs because programmable interconnections are required. Not only do these programmable interconnections prevent a more efficient routing, they also introduce longer propagation delays. By going to a 3-D design which allows flexible interconnect in every dimension we expect to be able to relieve routing congestion and shorten interconnect lengths dramatically, thus improving speed. The speed of an FPGA is a measure of the delay required to implement a function and to propagate signals to neighboring functions. The FPGA logic speed is often slow due to the interconnect delay. This delay can account for over 70% of the clock cycle period (2). Another problem with FPGA designs is the number of I/O connections available. According to Rent's Rule, the number of I/O pins needed on a given FPGA grows faster than the square root of the number of logic e lements. However, the number of perimeter bonding p ads that can fit along the die periphery only grows as the square root of the area. This means that for a given pad pitch (about 100 microns) and logic element pitch, there will be a die size beyond which the demand for I/O far exceeds the supply, in which case the device becomes pin limited. Experience with existing FPGAs shows that this results in low logic element utilization. Others have proposed u sing multichip module technology (MCMs), area-I/O, and optical interconnections to address some of these issues. These technologies all require that interconnections between chips or layers go through I/O pads and solder bumps. The geometries of solder bumps are on the order of 100 microns, an order of magnitude larger than our interconnections. In addition, I/O pads plus s older bumps are inherently more power hungry and complex than our technology which uses aluminum to interconnect chip layers.
Year
DOI
Venue
1997
10.1007/3-540-63465-7_207
FPL
Keywords
Field
DocType
dimensional fpga architecture,design tool,propagation delay,chip,three dimensional,three dimensions,3 dimensional
Computer architecture,Architecture,Applications architecture,Computer science,Parallel computing,Field-programmable gate array,Chip,Logic block,Systems architecture,Integrated circuit,Very-large-scale integration,Embedded system
Conference
ISBN
Citations 
PageRank 
3-540-63465-7
2
1.58
References 
Authors
5
4
Name
Order
Citations
PageRank
Miriam Leeser1791119.08
Waleed Meleis215718.29
Mankuan Michael Vai335300.56
Paul M. Zavracky4314.67