Paper Info
Title
A Framework for Static Analysis of VHDL Code
Abstract
Software in real time systems underlies strict timing con- straints. These are among others hard deadlines regarding the worst-case execution time (WCET) of the application. Thus, the computation of a safe and precise WCET is a key issue1 for validating the behavior of safety-critical systems, e.g. the flight control system in avionics or the airbag con- trol software in the automotive industry. Saarland University and AbsInt Angewandte Informatik GmbH have developed a successful approach for comput- ing the WCET of a task. The resulting tool, called aiT, is based on the abstract interpretation (3, 4) of timing mod- els of the processor and its periphery. Such timing models are hand-crafted and therefore error-prone. Additionally the modeling requires a hard engineering effort, so that the development process is very time consuming. Because modern processors are synthesized from a formal hardware specification, e.g., in VHDL or VERILOG, the hand-crafted timing model can be developed by manually analyzing the processor specification. Due to the complexity of this step, there is a need for sup- port tools that ease the creation of analyzes on such specifi- cations. This paper introduces the primer work on a frame- work for static analyzes onVHDL.
Year
DOI
Venue
2007
10.4230/OASIcs.WCET.2007.1189
WCET
Keywords
Field
DocType
real time systems,automotive industry,development process,worst case execution time,static analysis
Abstract interpretation,Computer science,Avionics,Static analysis,Real-time computing,Software,Control system,VHDL,Verilog,Automotive industry,Embedded system
Conference
Citations 
PageRank 
References 
5
0.46
8
Authors
2
Name
Order
Citations
PageRank
Marc Schlickling11447.27
Markus Pister217110.84