Name
Abstract | ||
|---|---|---|
Circuits built using multi-valued fixed polarity Reed-Muller expansions based on Galois field arithmetic, in particular quaternary expansions over GF(4), normally display high efficiency in terms of power consumption, area, etc. However, security application specific gate level mapping shows inefficient results for uniform radix expansions. The idea of the research here is to consolidate binary and quaternary Galois field arithmetic within a single circuit in such a way that the mathematical representations can benefit down to the gate level model. A direct method to compute quaternary fixed polarity Reed-Muller expansions of mixed radix arguments is proposed and implemented in a synthesis tool. The results for the various types of power-balanced signal encoding catered for the security application are compared and analysed. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISMVL.2009.21 | ISMVL |
Keywords | Field | DocType |
security application specific gate,level mapping,uniform radix expansion,cryptographic circuits,polarity reed-muller expansion,galois field arithmetic,mixed radix argument,security application,mixed radix arguments,particular quaternary expansion,quaternary galois field arithmetic,quaternary reed-muller expansions,gate level model,galois field,mathematical representation,direct method,binary arithmetic,arithmetic,encoding,reed muller codes,cryptography,mathematical model,logic gates,data mining,logic synthesis,galois fields,logic circuits,binary codes,security,switches,probability density function,displays | Logic synthesis,Finite field,Logic gate,Computer science,Binary code,Arithmetic,Radix,Reed–Muller code,Mixed radix,Binary number | Conference |
Citations | PageRank | References |
2 | 0.45 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ashur Rafiev | 1 | 50 | 8.67 |
| Julian P. Murphy | 2 | 4 | 2.87 |
| Alex Yakovlev | 3 | 516 | 64.23 |