Paper Info
Title
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Abstract
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression \cite{TenLectures, Shapiro, Spiht}. However, the algorithms proposed in literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we present an efficient architecture for computing DWT of images, which is based on a partitioned approach for lossy image compression~\cite{Ritter}. The architecture achieves its computational power by using pipelining and taking advantage of the flexible memory configurations available in FPGA's.
Year
DOI
Venue
2001
10.1145/360276.360350
FPGA
Keywords
Field
DocType
pipelined architecture,efficient technique,wavelet transformation,pipelining,architecture,lossy image compression,whole image,partitioned dwt,embedded zero tree coding,random access,efficient architecture,external memory,xilinx,image compression,algorithms unsuitable,extensive access,flexible memory,field programmable gate arrays,fpga,wavelet transform,discrete wavelet transform,field programmable gate array
Pipeline (computing),Set partitioning in hierarchical trees,Lossy compression,Computer science,Parallel computing,Image compression,Random access,Encoding (memory),Wavelet,Auxiliary memory
Conference
ISBN
Citations 
PageRank 
1-58113-341-3
16
1.25
References 
Authors
3
2
Name
Order
Citations
PageRank
Jörg Ritter1162.26
P. Molitor221118.50