Paper Info
Title
A Row-Parallel 8$\,\times\,$ 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation
Abstract
n algebraic integer (AI)-based time-multiplexed row-parallel architecture and two final reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row–column transforms, leading to an 8$\,\times\,$8 2-D DCT that is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on: 1) optimized Dempster–Macleod multipliers, and 2) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on field-programmable gate array (FPGA) chip. Six designs, for 4-bit and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented, and measured. The maximum clock rate and block rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of $8\times 307.787\approx 2.462~{\rm GHz}$ if eventually embedded in a real-time video-processing system. The equivalent frame rate is about 1187.35 Hz for the image size of 1920 $\,\times\,$1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.
Year
DOI
Venue
2012
10.1109/TCSVT.2011.2181232
IEEE Transactions on Circuits and Systems for Video Technology
Keywords
Field
DocType
discrete cosine transform,algebraic integer,field programmable gate array,noise,encoding,artificial intelligent,quantization noise,field programmable gate arrays,computer architecture,artificial intelligence,quantization,clock rate,video processing,chip,real time,quantization error,very large scale integration
Computer science,Discrete cosine transform,Artificial intelligence,Very-large-scale integration,Computer vision,Parallel computing,Field-programmable gate array,Algorithm,Chip,Gate array,Frame rate,Quantization (signal processing),Clock rate
Journal
Volume
Issue
ISSN
22
6
IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 6, pp. 915--929, 2012
Citations 
PageRank 
References 
8
0.54
24
Authors
7
Name
Order
Citations
PageRank
Arjuna Madanayake124253.31
Renato J. Cintra221826.82
Denis Onen3151.81
Vassil S. Dimitrov427431.85
Nilanka Rajapaksha5233.98
Leonard T. Bruton622032.12
Amila Edirisuriya7302.98