Name
Abstract | ||
|---|---|---|
In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined ... |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/s10836-005-5290-y | J. Electronic Testing |
Keywords | Field | DocType |
TPG,nonlinear,CA,prohibited pattern set | Cellular automaton,Partial scan,Vlsi chip,Nonlinear system,Digital pattern generator,Computer science,Algorithm,Real-time computing,Electronic engineering,Time complexity,Very-large-scale integration,Circuit under test | Journal |
Volume | Issue | ISSN |
21 | 1 | 0923-8174 |
Citations | PageRank | References |
5 | 0.85 | 10 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sukanta Das | 1 | 100 | 25.66 |
| Anirban Kundu | 2 | 75 | 15.44 |
| Biplab K. Sikdar | 3 | 217 | 40.85 |
| P. Pal Chaudhuri | 4 | 490 | 53.23 |