Name
Title | ||
|---|---|---|
A Finite Field Processor Employing Dual Parallel Datapath For High-Speed/Low-Power Rs-Ecc Applications |
Abstract | ||
|---|---|---|
We suggest a finite field processor for Reed-Solomon decoder which can be used for next generation DVDP/ROM, HD-DVD applications. Suggested processor implements Massey-Berlekamp's FSR synthesis algorithm which solve newton's identity to find the coefficients of error locator polynomial. By employing SIMD-like dual parallel pipelined datapath which exploited the characteristic of the needed computation of FSR algorithm, suggested processor shows about 2 times throughput at the same clock frequency compared with single pipelined datapath. Furthermore, it was implemented as a programmable processor rather than dedicated architecture to a specific error numbers and the length of codeword, it has flexibility and extensibility regardless of the number of correctable errors/erasures and the length of codeword. Suggested processor shows high-speed capability up to 320MHz if implemented using 0.35 mum technology. And also, this highspeed nature can be traded for lower-power consumption unless the aim of application is high-speed explicitly by reducing clock rate. |
Year | Venue | DocType |
|---|---|---|
2000 | 2000 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, PROCEEDINGS VOLS I-III | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyung-Joon Kwon | 1 | 0 | 0.68 |
| Youngbeom Jang | 2 | 0 | 1.35 |
| Bangwon Lee | 3 | 0 | 0.34 |